Bottom lead semiconductor chip package
US6043430A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/07802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bottom lead package is capable of increasing a memory capacity for a mounting position on a mother board by stacking several semiconductor packages such that exposed surfaces of leads on upper and lower surfaces of the package are aligned. The package includes a semiconductor chip, a plurality of lower leads attached to the lower side of the chip by an adhesive, a plurality of upper leads attached to the upper side of the chip by an adhesive and to the upper surfaces of the lower leads, wherein metal wires electrically connect the upper leads with a plurality of chip pads formed on the chip, and wherein a molding section packages the chip, the metal wires and the upper and lower leads, such that the upper and lower surfaces of the upper and lower leads, respectively, are externally exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.