Method for testing integrated circuits
US6043670A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Dec 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/323
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes a technique for testing packaged or unpackaged IC devices in which the devices are aligned and placed onto a tacky layer of an anisotropic conductive medium (ACM). The tacky ACM layer provides the necessary electrical contact to the IC device while under test, and also preserves the alignment of the IC device during movement between stations. When electrical testing of the IC device is completed the IC device packages are lifted free of the tacky layer and permanently bonded to an interconnection substrate. In one embodiment the test interconnection substrate is a replica of the permanent interconnection substrate. In another mode of practicing the invention the test interconnection substrate is the actual permanent interconnection substrate, and the IC device is bonded in situ after electrical testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.