5V tolerant I/O buffer
US6043680A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Feb 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its output node, while operating with a 3 volt power supply. This is achieved by inserting an extra p-channel transistor in series with the existing p-channel transistor. The extra p-channel transistor and its parasitic diode are wired so that they will not conduct, i.e. the extra transistor is off and the parasitic diode is back-biased, when a 5 volt input signal is applied to the output of the tristate input/output buffer. Two additional transistors are used to control the on/off state of the extra p-channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.