Multiplexed synchronization circuits for switching frequency synthesized signals
US6043693A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Jun 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock and a second slave clock, respectively, from the common master clock. A third multiplexer and a fourth multiplexer are configured as a divide-by-n circuit for providing a third slave clock that is a divided version of the second slave clock. A fifth multiplexer provides a matching delay to preserve the synchronization between the first slave clock and the other slave clocks. A sixth multiplexer is used to select between the second slave clock and the third slave clock in response to a select signal. A flip-flop may be used to provide the select signal and to guard against false selection of slave clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.