Selectable write precompensation in a direct access storage device (DASD)
US6043942A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Oct 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/09
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for write precompensation in a direct access storage device are provided. A data write encoder generates a data signal to be written. A write precompensation delay circuit is coupled to the data encoder for receiving and delaying the data signal. The write precompensation delay circuit includes a first delay path and a second delay path in parallel with the first delay path. The first delay path and the second delay path have different delay values. In one arrangement, both the first delay path and the second delay path include a plurality of delay cells connected together in a chain. The delay cells of the first delay path have a first predetermined delay value and the delay cells of the second delay path have a second predetermined delay value. A ratio of the second predetermined delay value to the first predetermined value is set equal to one of approximately 3/2, 4/3, 5/4, 6/5, or 7/6. In another arrangement, a first delay path includes a plurality of delay cells connected together in a chain and a plurality of delay cells connected in parallel provide multiple parallel delay paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.