Delta sigma PLL with low jitter
US6044124A · kind A · utility
65Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Aug 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/6143
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase lock loop circuit for a digital radio generates the sampling frequency for sampling an incoming signal by storing the samples of the incoming signal in an accumulator at a first frequency. The accumulator is unloaded at the sampling frequency. A microprocessor monitors the rate in which the samples are stored in the accumulator and provides a switching signal to vary the sampling frequency in small increments to prevent the accumulator from overflowing or underflowing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.