Method and apparatus for encoding valid and invalid states in a cache with an invalid pattern
US6044441A · kind A · utility
11Cited by
10References
8Claims
0Family size
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Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller unit includes an address comparator unit for comparing an address to be accessed in memory with a tag address. An invalid pattern comparator is coupled to the address comparator. The invalid pattern comparator operates to compare the tag address with an invalid pattern. A qualifier unit is coupled to the address comparator and the invalid pattern comparator. The qualifier unit outputs a signal when the address to be accessed in the memory matches the tag address in the address tag and the address tag does not match the invalid pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.