Processor having multiple datapath instances
US6044448A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Dec 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a sliceable architecture wherein a slice is the minimum configuration of the processor datapath. The processor can instantiate multiple slices and each slice has a separate datapath. The total processor datapath is the sum of the number of slices multiplied by the width of a slice. Accordingly, all general purpose registers in the processor are as wide as the total datapath. A program executing on the processor can determine the maximum number of slices available in a particular processor by reading a register. In addition, a program can select the number of slices it will use by writing to a different register. The processor replicates control signals for each active slice in the processor and supports instructions for transferring data among the slices. Furthermore, the processor supports a set of instructions for fetching and storing data between multiple slices and the memory. The effective addresses of the fetch and store instructions can either be aligned or misaligned with respect to slice boundaries and doubleword boundaries in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.