State machine controller capable of producing result per clock cycle using wait/no wait and empty signals to control the advancing of data in pipeline
US6044457A · kind A · utility
1Cited by
1References
8Claims
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Key dates
| Filing date | Apr 3, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Apr 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A state machine controller which can be used for fetching data for a real-time computer image generation system and which provides valid data for each clock interval of a system control clock. The state machine controller can produce a result per clock pulse, schedule new data to be processed before completion of the processing of previous data to prevent bubbles or interruptions in the data pipeline, and can stop and maintain its output if a hold is applied from a later pipeline stage, and can resume one clock operation on the clock pulse when the hold is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.