System for monitoring program flow utilizing fixwords stored sequentially to opcodes
US6044458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a control flow monitor (CFM) checker for verifying a sequence of instructions performed by a pipelined processor (101). The CFM checker provides fail safe assurance against run-time errors in the sequence of instructions performed by a processor. The CFM checker verifies instruction sequence during run-time within 32 instruction cycles. The processing system provides an improved system and method having a CFM checker which minimizes wasted instruction cycles when performing branch instructions in a software program. Using a prefetch capability of an instruction pipeline and storing fixwords sequentially in memory, eliminates unnecessary instructions to fetch fixword values from external tables, thereby saving instructions and instruction cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.