System and method for PC-relative address generation in a microprocessor with a pipeline architecture
US6044460A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Jan 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is provided which performs relative addressing using the exception program counter. In one embodiment, a pipelined processor is provided with an exception program counter (EPC) register chain for tracking exception re-entry points in the instruction stream, and the instruction pipeline is provided with access to at least one of the registers in the register chain. The pipeline includes a fetch stage, a decode stage, and an execute stage. The exception PC register is identified by the decode stage as an operand in a memory access instruction for the execute stage to operate on. The execute stage then adds the contents of the exception PC register to the contents of a processor register or to a literal value to determine a target memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.