Semiconductor device capable of operating stably with reduced power consumption
US6046627A · kind A · utility
93Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1998 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Feb 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/073
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.