Ferroelectric memory and screening method therefor
US6046926A · kind A · utility
34Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory has a memory cell screening test circuit connected to bit lines through switching transistors. In screening, at least one word line is selected, and data is simultaneously written in all memory cells connected to this word line. Since data is not restored after the rewrite, all FRAM cells can be screened under the same condition. By this circuit, a memory cell having a write failure according to the imprint characteristics inherent to the ferroelectric memory is screened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.