Memory device with two ferroelectric capacitors per one cell
US6046929A · kind A · utility
19Cited by
1References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1999 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Mar 31, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The source region and gate electrode of a field effect transistor including a drain region and a gate electrode in addition to the source region are connected by a first ferroelectric capacitor. The drain region and gate electrode are connected by a second ferroelectric capacitor. A ferroelectric memory device suitable for high integration is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.