Method and apparatus for reducing data loss in data transfer devices
US6046982A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1997 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Mar 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5679
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The input bandwidth of a data transfer device is increased by altering the conventional memory arbitration method in which a data cell is stored and a data cell is forwarded during each data transfer cycle. The input data rate is monitored and when the input data rate exceeds the maximum average throughput of the memory, the outcome of the memory arbitration cycle is changed so that the memory arbitration cycle consists of two stores (memory write operations) instead of one store and one forward (memory read operation.) In effect, the input memory arbitration process steals cycles from the output memory arbitration process when the input load exceeds that of the maximum average memory throughput. In accordance with one embodiment, the input data rate is monitored by examining input port FIFO buffers for the presence of data cells waiting for storage. Based on the results of the FIFO monitoring and the outcome of the current port arbitration cycle, a decision is made on the following port arbitration cycle whether to change the normal memory arbitration pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.