Bare die carrier
US6049215A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1995 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Oct 12, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A bare semiconductor circuit die carrier is provided for use in the test of semiconductor circuits, the carrier, comprising: a substrate defining an opening and an outer perimeter; a multiplicity of I/O pads disposed about the perimeter; an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed in a polymer dielectric; wherein the interconnect circuit overlays a top surface of the substrate and extends across the opening so as to form a flexible membrane that spans the opening; a multiplicity of die contact pads connected to the conductors are disposed about the flexible membrane with particles deposited on the die contact pads; a fence upstanding from the membrane and sized to receive a test die; a top cap that rests upon the die when the die is received within the fence; a bottom cap that rests against a bottom surface of the substrate; and a fastener for securing the top cap to the bottom cap with the die disposed therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.