Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
US6049223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 1996 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Jul 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.