Clock synchronous semiconductor memory device capable of preventing outputting of invalid data
US6049488A · kind A · utility
12Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 27, 1998 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Jul 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gate circuit is turned on in synchronization with an internal clock signal at a timing faster than activation of an output buffer circuit, and internal data is transmitted from the gate circuit to an output buffer circuit externally outputting data. Generation of an internal clock signal is stopped at a timing faster than deactivation of the output buffer circuit, and the gate circuit is set to the latching state. According such arrangement, output of invalid data is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.