Failure-data storage system
US6049898A · kind A · utility
2Cited by
13References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1998 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Feb 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31935
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A failure-data storage system is disclosed which is able to prepare data accumulated from a multiple data bit device test. Failure-data from the memory tester 1 is, before being stored in memory IC 6, logically added to one previous cycle failure-data with the same address by OR gate 12, and the result is input to F/F 13. The output of the F/F 13 is input to memory IC 6 when 3 state buffer 14 is in an enabled state and is fed back to the OR gate 12. Furthermore, each of the data bit of memory IC has data controller 10-1, 10-2, 10-3, and 10-4 as explained above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.