Memory integrated circuit and methods for manufacturing the same
US6051461A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jun 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A memory integrated circuit which is driven with a low power and reduced the cell area and a method for manufacturing the same. A plurality of active regions having an H-shape with four source regions and common drain region are formed on a semiconductor substrate. Four word lines each having a different source correspondingly pass through each of the four source regions of an active region, thereby forming four transistors driven, independently. These four transistors are designed so as to share one bit line, thereby reducing the driving voltage of the transistor to 1/4 Vcc. With a low power driving source, four transistors and a capacitor are formed on a small area to thereby reduce the cell size to 33% and even more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.