Method for manufacturing capacitor of semiconductor memory device
US6051476A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method to reduce step difference of a cell region and a peripheral region, and to increase the capacitance. A first intermetal insulating layer, a planarization layer and a second intermetal insulating layer are formed successively on the semiconductor layer including a storage node. A contact hole is formed by etching the first intermetal insulating layer, the planarization layer and the second intermetal insulating layer so that a selected portion of the storage node is exposed. A photoresist pattern in which a wave of saw-teeth shape is formed at sidewalls, is formed on the second intermetal insulating layer so as to fill the contact hole. Spacers are formed at both sidewalls of the photoresist pattern in which the wave of saw-teeth shape is formed. Herein, a wave of saw-teeth shape is formed at inner surfaces of the spacer owing to both sidewalls of the photoresist pattern. The photoresist pattern in which the waves of saw-teeth shape are formed at sidewalls thereof, is removed. A storage node electrode is formed by filling inside of the contact hole and between the spacers with a doped polysilicon layer. Herein, a wave of saw-teeth shape is formed at sidewalls o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.