Semiconductor devices utilizing silicide reaction
US6051851A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 26, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Aug 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cheap semiconductor memory devices are provided so as to enable high-speed writing and reading but rarely to malfunction, thus being high in reliability. In a semiconductor device which comprises a plurality of cells each having a semiconductor layer between a pair of conductors, at least one of the pair of conductors is made of a metal, and the semiconductor layer comprises an amorphous silicon that can form a silicide region with the metal as reacting at a reaction rate of not less than 10 m/sec. Another device is characterized in that the semiconductor layer is an amorphous silicon, in that at least one of the pair of conductors is made of a metal silicide-reacting with the amorphous silicon, and in that the silicide region formed is conic. Another device is characterized in that the semiconductor layer is an amorphous silicon, in that at least one of the pair of conductors is formed of a metal silicide-reacting with the amorphous silicon, and in that a film-formed surface is produced without being exposed to an oxide atmosphere, between a step of forming the amorphus silicon and a step of forming the metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.