Fractional period delay circuit
US6052011A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 10, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Nov 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master clock to form the first timing signal. The fractional period delay circuit has plurality of adjustable delay lines. Each adjustable delay line is connected to the master timing signal to delay the master timing A delay adjustment input will modify the delay of the adjustable delay circuit. The fractional period delay circuit further has a plurality of phase difference detectors connected to the output of the first delay line and to the output of one of the plurality of adjustable delay lines. The phase difference detector will create a difference signal indicating a difference in phase between the first timing signal and one of the delayed timing signals. A plurality of sequence timing signals are created in a is timing sequence generator. A phase correction calculators is connected to a phase difference detector and the timing sequence generator to calculate a delay adjustment signal. The delay adjustment signal is an error signal i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.