Serial to parallel converter enabled by multiplexed flip-flop counters
US6052073A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Mar 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.