Inverter input noise suppression circuit
US6052298A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1999 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Mar 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/15
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A noise suppression circuit for use with a DC/DC converter having an output and an input responsive at least in part to the output of the converter is provided. The noise suppression circuit includes multiple parallel feedback loops, wherein the first feedback sets the steady state nominal output voltage, the second feedback loop prevents the output voltage from exceeding a predefined high voltage level, and the third feedback loop prevents the output voltage from decreasing below a predefined low voltage level. In some embodiments, the first, second, and third feedback loops comprise a operational amplifier, a diode, and an internal feedback loop, wherein the internal feedback loops of each of these loops share a common node. The common node configuration provides the circuit with quick transitions between output voltage states and dynamic regulation of the DC/DC converter output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.