Repairable semiconductor memory circuit having parrel redundancy replacement wherein redundancy elements replace failed elements
US6052318A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.