Memory circuit including reduced area sense amplifier circuitry
US6052323A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 1999 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jul 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit (10) provides reduced array sense amplifier circuitry (20, 22) for a memory cell array (24, 26, 28, 30), which has a plurality of memory cells (340) for electrically storing data. A plurality of bitlines (260) are associated with a memory cell array (26) for carrying data to and from the memory cells therein. At least one sense amplifier circuit (16) includes circuitry (332, 334) for addressing selected memory cells via column select lines, and for communicating with an external source of address signals. A local sense amplifier circuit (20, 22) includes circuitry (262, 266) for communicating with the sense amplifier circuit through the selected bitlines. The local sense amplifier circuit also includes circuitry (234, 238) for communicating with other bitlines (232, 236) for addressing other memory cells (28), and further for transmitting data to and from the other memory cells along the selected bitlines, in cooperation with the sense amplifier (16).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.