Output circuit and synchronous semiconductor memory device having a function of preventing output of invalid data
US6052329A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 21, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jul 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output circuit and a synchronous semiconductor memory device according to the invention suppress output of invalid data, and perform data output with exact timings. The synchronous semiconductor memory device includes a plurality of output buffers provided correspondingly to data I/O terminals, a plurality of data transfer latch circuits and a plurality of output control signal latch circuits. Data transfer latch circuit transfers data read from a memory cell to the corresponding output buffer in response to an internal clock signal. The output control signal latch circuit issues an output control signal to the corresponding output buffer in synchronization with the internal clock signal. Thereby, an output timing of each output buffer can be controlled independently of the other output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.