Method and apparatus in a packet routing switch for controlling access at different data rates to a shared memory
US6052738A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling access to a shared memory in a network system is described. The apparatus includes at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width. Each fast input port interface comprises a fast interface register configured to temporarily store the data and address information. Each fast input port interface further comprises a command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory. The apparatus also includes at least one slow port interface circuit, each configured to receive data, address, and command information from a network client at a second data rate in segments of the first width and transmit the data, address, and command information to a storage circuit that is shared among the slow port interface circuit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.