Multiprocessor system memory unit with split bus and method for controlling access to the memory unit
US6052763A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit and method for using the memory unit in a tightly coupled multiprocessor system having a split model bus is configured to perform an atomic transaction that is carried out in a synchronous mode on the basis of semaphore variables or lock variables. A decoder is included in the memory unit and generates an atomic address space and a conventional address space in an address space of a RAM portion of the memory unit. An identifier unit identifies whether a memory access request is from a bus master and is for an atomic address space or for the conventional and address space. Based on whether the access request is for the atomic address space or the conventional address space controls an atomic transaction mode-shifting unit to shift between an atomic transaction mode of operation and a normal mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.