Microprocessor with pipeline synchronization
US6052771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jan 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of the processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of the sequential stream of instructions by the first processing element it becomes beneficial to have the second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of the computer system which is determined by a combination of the states of the first and second processing elements. The second processor will have more pipeline stages than the first in order processor to feed the first processor and reduce the finite cache penalty and increase performance. The processing and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.