Fast destaging method using parity engine
US6052822A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the fast destaging method using a parity engine, and more particularly to the fast destaging method for constituting and administering the cache of disk array in order to minimize lowering of write performance which occurs in high-speed disk array controller using VRAM parity engine. According to the invention, the disk cache is composed of the read cache, the write cache and the destaging cache. The write caching is processed as being divided into the write cache and the destaging cache. The destaging cache, which has just one more block for mid parity to its data block, uses less memory and enables the write cache to be allocated with more blocks, and thereby it can improve hit ratio of cache. Write requests are first stored on the write cache, and if the write cache is full, they move blocks that would be least used thereafter into the destaging cache. Once destaging is requested, it is practicable with one parity calculation and two write operations by selecting blocks that is least recently used. Also in destaging, block parity calculation can increase its speed and relieve the processor burden by using a VRAM based parity engine which has its …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.