Process-insensitive controllable CMOS delay line
US6054884A · kind A · utility
16Cited by
2References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 23, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Jan 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay cell for use in binary delay line which includes a delay circuit having N outputs where N.gtoreq.2, each delay circuit coupled to an input through N-1 serially connected unit cells. For each output there are P unit cells having a unit delay of t.sub.P0 and N-1-P unit cells having a unit delay of t.sub.p1. The N outputs are ordered such that each output other than the first is delayed with respect to an immediately preceding output by t.sub.p1 -t.sub.p0, and P goes in succession from N-1 to 0 in unit steps. Each value of P corresponds to only one of the N outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.