Automatic gain control circuit with low distortion
US6054899A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1999 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Jan 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An automatic gain control circuit is described, comprising: a resistance control node, a first field-effect transistor, a second field-effect transistor, an inductor, a first resistor, a second resistor, a first capacitor, and a second capacitor. The inductor is connected in series with the field-effect transistors. The first resistor is connected between the gate of the first field-effect transistor and the resistance control node while the second resistor is connected between the gate of the second field-effect transistor and the resistance control node. The first capacitor is connected between the gate and drain of the first field-effect transistor, whereas the second capacitor is connected between the gate and source of the second field-effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.