Semiconductor memory device with simultaneously activated elements and a redundancy scheme thereof
US6055197A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device, assuming that the ratio of a memory capacity of a region of a memory array per one of elements, which are simultaneously activated in the memory array in which x elements (x is an integer of two or more) are simultaneously activated and which is divided into a plurality of repair regions, each of which has at least two elements, to a memory capacity in one of the repair regions corresponding to one of spare element groups is y (y is an integer of one or more), each of the repair regions is designed so that a plurality of elements are simultaneously activated in its own repair region, and each of the spare element groups is designed so that the number of spare elements simultaneously activated in each of the spare element groups is one. Thus, it is possible to effectively reduce electric current consumption in the total of redundant control circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.