Architecture for a dual segment dual speed repeater
US6055241A · kind A · utility
9Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1997 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Nov 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.