Apparatus and method for matrix multiplication
US6055556A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1997 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Aug 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system (400) alternatively performs real matrix operation in a first mode or performs complex matrix multiplication in a second mode. One input matrix (e.g., {B}) stays in a plurality of memory fields (430-k), while the other input matrix (e.g., {A}) is loaded into a plurality of registers (410-k). Parallel operating groups (405-k, 409-(k+1)) combine elements of {A} with elements of {B}. The groups (405-k, 409-(k+1)) comprise the memory fields (430-k), the registers (410-k) as well as computational units (440-k), switches (420-k) and adder units (460-k). The adder units (460-k) are configured by the switches (420-k) to operate as adders or to operate as accumulators, depending on the mode. Adders provide intermediate results and accumulators accumulate these intermediate results (e.g., Sum) to elements of the resulting matrix {C}. For complex multiplication, real (Re) and imaginary (Im) parts of matrix elements are in processed in adjacent groups. The system (400) uses logarithmic representations of the matrix elements and further comprises a log converter (490) and a plurality of inverse log converters (450-k).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.