Integrated circuit SCSI I/O cell having signal assertion edge triggered timed glitch filter that defines a strobe masking period to protect the contents of data latches
US6055587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit, configured for connection to an SCSI bus includes a strobe assertion edge triggered glitch filter. Input data latches are controlled by the strobe assertion edge gated with a strobe enable signal and the inverted and delayed Q output of a flip-flop. Once a valid strobe assertion edge is detected, it is used latch data bus signals into the data latches. Following a defined delay period through a delay stage, the data latch strobe is masked from any further transition until the strobe enable signal is again affirmatively asserted by an SR latch. The masking period is defined upon receipt of a valid strobe assertion edge and maintained for a first period by the combination of the SR latch, a flip-flop and a delay stage. The latch strobe mask is maintained for a second period by a strobe masking extension circuit made up of series-connected flip-flops. The strobe mask extension period is determined by a sampling or reference clock frequency which propagates a signal through the flip-flops to subsequently cause the SR latch to affirmatively assert a strobe enable signal just before the expected arrival of a next valid assertion edge of the strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.