Control register bus access through a standardized test access port
US6055656A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1995 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | May 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.