Method of making peripheral low inductance interconnects with reduced contamination
US6057027A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24917
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for making a circuit device having at least one peripheral interconnect for electrically connecting the device to another circuit device on a motherboard, includes forming at least one opening in a substrate, the opening having an inner surface extending between first and second major surfaces of the substrate. The inner surface of the opening and portions of the major surfaces adjacent the opening are coated with electrically conductive material. Electrically conductive material is removed from opposing regions of the inner surface of the opening prior to plating and then, after plating, the substrate is cut in a line extending across opposing regions to expose the coated and plated inner surface as the peripheral electrical interconnect. The method produces interconnects with reduced contamination by conductive particulates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.