Chip carrier having a specific power join distribution structure
US6057596A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Oct 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip carrier for carrying a chip is disclosed. The chip carrier includes a substrate having a first surface for mounting therein the chip wherein the substrate has a plurality of through holes and a plurality of conducting lines, a plurality of grounded joints set at a corresponding position of a second surface of the substrate under the chip and electrically connected to the chip by the plurality of conducting lines through the plurality of through holes for grounding, a plurality of signal joints surrounding the plurality of grounded joints on the second surface of the substrate and electrically connected to the chip by the plurality of conducting lines through the plurality of through holes for transmitting a series of signals, and a plurality of power joints set between the grounded joints and the signal joints and electrically connected to the chip by the plurality of conducting lines through the plurality of through holes for energizing the chip wherein there exists spaces among the ground joints, the signal joints, and the power joints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.