Apparatus and method for clocking digital and analog circuits on a common substrate to enhance digital operation and reduce analog sampling error
US6057791A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 18, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Feb 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for clocking digital and analog circuits on a common substrate is provided. The apparatus and method serves to reduce digitally derived noise at select times during which the analog input signal is sampled. Analog sampling error is thereby reduced while, at the same time, the digital clocking signal maintains maximum frequency. Digitally derived noise is substantially eliminated near the latter portion of each sampling interval to ensure an accurate sampled value exists at the culmination of that interval. During the earlier portion of each sampling interval, digital clocking pulses are maintained at a high frequency so as to enhance processing speeds. It is determined that only the latter portion of each sample interval is critical to the reduction of sampling error. Furthermore, the digital clocking pulses occur a non-power-of-two factor to ensure tonal noise is not coupled into the analog circuit frequency band of interest.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.