Shielded bit line sensing scheme for nonvolatile semiconductor memory
US6058044A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.