Computation apparatus and method
US6058409A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Aug 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computation apparatus such as a Fast Fourier Transform (FFT) apparatus which processes ordered sets of data in a computation unit (4, 24) operating according to a high-speed clock includes an input buffer (1, 21) arranged to accept data in synchronism with a relatively low-speed clock, and an output buffer (6, 26) arranged to discharge the data in synchronism with the low-speed clock. The apparatus includes an internal memory (3, 23) as well as means such as selectors (2, 22) and (5, 25) for transferring data in synchronism with the high-speed clock from the input buffer to the computation unit or the memory; between the computation unit and the memory; and from the computation unit or the memory to the output buffer. The transferring means is arranged to reorder the data, preferably in reverse-digit sequence, during transfer from the input buffer or during transfer to the output buffer. This avoids the need for a separate reordering memory at the input end or output end of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.