Fault tolerant serial arbitration system
US6058449A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Jul 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/374
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial arbitration system utilizes an arbitration token containing a start bit, a request bit, a set of priority bits, and an error detection bit. The arbitration token is sent to each of the other processors (20, 21, 22) and is used to arbitrate control of a shared bus (38). A processor indicates that it is the master (20) by setting the start bit (120). It enters an arbitration by setting the request bit (124). The set of priority bits (134) contains a binary priority value encoded in bit major order. This format allows an optimized parallel comparison (128, 130) of the priority values for each of the requesting processors a bit at a time. Finally, processors drop out of the arbitration upon detecting (136) a parity error in an arbitration token received from another processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.