Method and apparatus for refreshing a non-clocked memory
US6058451A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimized memory refresh scheme controls and reduces instantaneous power consumption and power-related noise during DRAM refresh. In the optimized refresh implementation the DRAM is refreshed using a selectable overlap Column Address Select (CAS) before Row Address Select (RAS) refresh mode. A refresh interface between a host port and the memory system is over two bussed signals comprised of a Refresh Enable signal (Refresh.sub.-- Enable) and a Refresh Strobe pulse train (Refresh.sub.-- Strobe). Refresh.sub.-- Enable is issued by the host port to define a refresh operation. Refresh.sub.-- Strobe is a pulse train generated by the host port which is used as a clock for a sequential refresh sequencer. A refresh sequencer issues selectably timed column address refresh and row address refresh signals according to which the memory banks can all be selectably refreshed substantially in parallel, or with a predetermined selected level of overlap. Optimized skewing can be implemented to minimize the time for refresh. Refreshing of different memory banks can be selectably overlapped to provide acceptable current and noise profiles during refresh.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.