Method and system for fault-handling to improve reliability of a data-processing system
US6058491A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1695
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a system bus, a first processor is utilized to produce a first output. The second processor, also coupled to the system bus, is utilized to produce a second output. During the operation of the computer system, the second processor operates at the same clock speed as the first processor and lags behind the first processor. The comparator is utilized to compare the first and second output such that an operation will be retried if the first output is not the same as the second output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.