Error correcting method and device
US6058499A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Reed-Solomon encoded data read from a CD-ROM, DVD-ROM, or other recording or transmission source is error corrected at high speed in an apparatus that employs a pair of byte-wide error correcting sub-circuits operating substantially in parallel. An MSB plane of a sector of received Reed-Solomon data is processed in one error correcting circuit while an LSB plane of the same sector is processed in the other circuit. Errors are corrected in each sub-circuit as may be necessary, and selection circuitry selects the corrected data, or non-corrected data, as appropriate, for each plane, and then combines the selected data to form the word-wide output data for transmission, e.g. to a host processor. The operation is pipelined and, although only one error is corrected at a time, the invention provides word-wide, error-corrected data at a data rate only a few clock cycles slower than prior art byte serial EC technology, so the effective transmission rate to the host is substantially improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.