Control of parallelism during semiconductor die attach
US6059917A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1996 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Dec 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/07802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention is to a mounting device (12) and to a method of mounting a semiconductor die (11) to a mounting surface (10) to ensure that the die (11) is in a plane parallel to the mounting surface (10). An intermediate woven mounting device (12) having two parallel faces and having a plurality of co-planer mounting points (13a and 14a) on each of the parallel faces is placed on a semiconductor mounting surface (10) and the semiconductor die (11) is placed on the intermediate device. Along with a die attach adhesive, heat and pressure is applied to secure the semiconductor die (11) and intermediate mounting device (12) to the mounting surface (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.