MOS transistors with improved gate dielectrics
US6060406A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | May 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes silicon MOS devices with gate dielectrics having the composition Ta.sub.1-x Al.sub.x O.sub.y, where x is 0.03-0.7 and y is 1.5-3, Ta.sub.1-x Si.sub.x O.sub.y, where x is 0.05-0.15, and y is 1.5-3, and Ta.sub.1-x-z Al.sub.x Si.sub.z O.sub.y, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO.sub.2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO.sub.2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.